Chip Size Estimation for SOC Design Space Exploration

At early design space exploration phases of architectures for systems on a chip (SOC) total costs of silicon are of high interest. An accurate chip size estimation needs detailed knowledge of the transistor densities of a semiconductor process. This paper introduces a novel and simplified chip size estimator, which is independent of manufacturer specific process data. CMOS processes are characterized by only three parameters. These are the drawn gate length and the used numbers of metal layers for logic and for memories. A minimum possible chip size (bestcase) is evaluated from the numbers of transistors for logic and for memories, and from the number of pad cells. The chip size estimator has been derived from a comprehensive analysis of realized VLSI chips. It has been investigated and confirmed either for published VLSIs as well as for latest SOC designs with 221 million transistors and 333 million transistors. The proposed model contributes to analytical modeling of cost and performance tradeoffs of SOC concepts