Title :
State machine abstraction from circuit layouts using BDDs: applications in verification and synthesis
Author :
Kam, Timothy ; Subrahmanyam, P.A.
Author_Institution :
Dept. of Electron Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The authors discuss a formal technique for abstracting a finite state machine (FSM) from a transistor netlist, given information relating to clock signals and clo·cking methodology. The abstracted FSM is represented as a transition relation using binary decision diagrams (BDDs) and then converted into a synchronous sequential network. Both the relational and network representations are common starting points for various sequential synthesis and verification tools
Keywords :
asynchronous sequential logic; circuit layout CAD; finite state machines; formal verification; logic CAD; BDDs; circuit layouts; clock signals; finite state machine; network representations; sequential synthesis; sequential verification; state machine abstraction; synchronous sequential network; synthesis; transistor netlist; transition relation; verification; Adders; Boolean functions; Circuit simulation; Circuit synthesis; Clocks; Data mining; Data structures; Latches; Logic devices; Logic gates;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246259
