Hot-electron injection and trapping in the gate oxide of submicron DMOS transistors

Author

Manzini, S. ; Gallerano, A. ; Contiero, C.

Author_Institution

SGS-Thomson Microelectron., Milan, Italy

fYear

1998

fDate

3-6 Jun 1998

Firstpage

415

Lastpage

418

Abstract

The basic parameter controlling the hot-electron safe operating area of DMOS transistors integrable in submicron bipolar-CMOS-DMOS mixed processes is the series resistance of the n-type lightly-doped layer on the source side of the devices. The hot-electron-induced degradation in DMOS transistors is correlated with the hot-electron gate current, rather than with the substrate (p-body) current, and its measurement is a sensitive, nondestructive way to bypass long-term reliability tests

Keywords

BIMOS integrated circuits; dielectric thin films; electric current; electric resistance; electron traps; hot carriers; power MOSFET; power integrated circuits; semiconductor device testing; DMOS transistors; Si; SiO₂-Si; bipolar-CMOS-DMOS mixed processes; device source side; gate oxide; hot-electron gate current; hot-electron injection; hot-electron safe operating area; hot-electron trapping; hot-electron-induced degradation; n-type lightly-doped layer; reliability tests; series resistance; substrate p-body current; Current measurement; Degradation; Electrical resistance measurement; Lighting control; MOSFETs; Microelectronics; Nondestructive testing; Secondary generated hot electron injection; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on

Conference_Location

Kyoto

ISSN

1063-6854

Print_ISBN

0-7803-4752-8

Type

conf

DOI

10.1109/ISPSD.1998.702734

Filename

702734