Analysis of high current breakdown and UIS behavior of resurf LDMOS (RLDMOS) devices

Author

Pendharkar, Sameer ; Efland, Taylor ; Tsai, Chi-Yi

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1998

fDate

3-6 Jun 1998

Firstpage

419

Lastpage

422

Abstract

This work analyzes unclamped inductive switching (UIS) behavior of two types of 40 V resurf (reduced surface field) lateral diffused MOSFETs (RLDMOSFETs). It is shown that the addition of a deep buffer implant region on the drain side of the device increases the snap-back current limit as well as UIS robustness. It is also shown, using 2D simulation, that the failure current limit under UIS conditions is not the same as the current at which the parasitic BJT turns on

Keywords

electric breakdown; electric fields; failure analysis; fault currents; power MOSFET; semiconductor device models; semiconductor device reliability; semiconductor device testing; surface potential; switching; 2D simulation; 40 V; RLDMOS devices; RLDMOSFETs; UIS behavior; UIS conditions; UIS robustness; current breakdown; deep buffer implant region; device drain buffer implant region; failure current limit; parasitic BJT turn-on current; reduced surface field lateral diffused MOSFETs; resurf LDMOS devices; snap-back current; unclamped inductive switching; CMOS process; Doping; Electric breakdown; Implants; Instruments; MOSFETs; Robustness; Signal analysis; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on

Conference_Location

Kyoto

ISSN

1063-6854

Print_ISBN

0-7803-4752-8

Type

conf

DOI

10.1109/ISPSD.1998.702735

Filename

702735