An area efficient digital amplitude modulator in 90nm CMOS

Author

Chironi, V. ; Debaillie, B. ; Baschirotto, A. ; Craninckx, J. ; Ingels, M.

Author_Institution

Dept. of Innovation Eng., Univ. of Salento, Lecce, Italy

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

2219

Lastpage

2222

Abstract

This paper presents a digital amplitude modulator (DAM) for polar transmitter in 90 nm CMOS technology. It consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB error vector magnitudes (EVM) and 18% drain efficiency. The 8-bit are segmented addressed. This results in a very compact 0.007 mm² chip area.

Keywords

CMOS integrated circuits; OFDM modulation; interpolation; modulators; quadrature amplitude modulation; wireless LAN; 2-fold interpolation; CMOS; WLAN OFDM QAM modulation; amplitude code; continuous-time conversion; digital amplitude modulator; discrete-time conversion; error vector magnitudes; frequency 2.45 GHz; nonconstant envelope RF output; polar transmitter; size 90 nm; word length 8 bit; Amplitude modulation; CMOS technology; Digital modulation; Interpolation; OFDM; Power generation; Radio frequency; Shape; Transmitters; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537206

Filename

5537206