DocumentCode
3375573
Title
On clustering of undetectable transition faults in standard-scan circuits
Author
Pomeranz, Irith
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
2011
fDate
1-5 May 2011
Firstpage
128
Lastpage
133
Abstract
Transition faults are used for modeling delay defects. A comparison between transition faults and single stuck-at faults indicates that many more transition faults than single stuck-at faults in standard-scan circuits are undetectable. Furthermore, this paper shows that undetectable transition faults in benchmark circuits appear in larger clusters than single stuck-at faults, where a cluster consists of several undetectable faults that are included in the same connected subcircuit. This implies that test sets for transition faults do not cover delay defects uniformly across the circuit. The paper studies the clustering of undetectable transition faults in standard-scan benchmark circuits by considering exhaustive as well as deterministic test sets. It defines double transition faults that provide targets for improving the coverage of subcircuits with undetectable transition faults, and presents the results of test generation.
Keywords
automatic test pattern generation; delay circuits; fault diagnosis; integrated circuit testing; logic testing; connected subcircuit; delay defects; deterministic test sets; single stuck-at faults; standard-scan benchmark circuits; standard-scan circuits; test generation; undetectable transition fault clustering; undetectable transition faults; Circuit faults; Logic gates; Double faults; scan circuits; transition faults; undetectable faults;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2011 IEEE 29th
Conference_Location
Dana Point, CA
ISSN
1093-0167
Print_ISBN
978-1-61284-657-6
Type
conf
DOI
10.1109/VTS.2011.5783772
Filename
5783772
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