Hierarchical generation of pin accurate SystemC models based on RF circuit schematics

This paper presents a method to generate pin accurate SystemC models based on the RF circuit schematics, using a SKILL based routine. This method addresses the verification and modeling of the analog/RF circuits in the event driven digital domain using SystemC, based on the same data base created by the circuit designer. The proposed method was employed to model a specific test case, comprising a phase locked loop in a RF receiver chain. The reliability of the SystemC models have been proven by comparing the simulation results with the Verilog-AMS(wreal) models. The pin accurate SystemC models were found to be well suited for top down design, virtual prototyping and verification in SoC implementation. Additionally, the SystemC models are very efficient regarding the simulation speed and flexibility to pass abstract data types with real numbers through the ports.