DocumentCode :
3375610
Title :
Training-based forming process for RRAM yield improvement
Author :
Shih, Hsiu-Chuan ; Chen, Ching-Yi ; Wu, Cheng-Wen ; Lin, Chih-He ; Sheu, Shyh-Shyuan
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2011
fDate :
1-5 May 2011
Firstpage :
146
Lastpage :
151
Abstract :
Over the past decade, the resistive memory device known as RRAM has been studied extensively in many ways, and many of its problems have been identified, discussed, and some solved. It is time to move from material, process, and device to circuit design and yield, in order to commercialize RRAM. However, as we move from resistive device to memory circuit, new problems do appear, partly because the operating conditions of resistive devices on real RRAM circuit differ from those in an experimental environment for single devices. In this paper, an over forming problem has been identified from our analysis, and we propose a solution based on training sequence. As a result, by solving the over forming problem, RRAM yield can be improved significantly.
Keywords :
integrated circuit design; integrated circuit yield; logic testing; random-access storage; RRAM yield improvement; circuit design; memory circuit; operating conditions; over forming problem; real RRAM circuit; resistive memory device; single devices; training sequence; training-based forming process; Circuit faults; Electrical resistance measurement; Resistance; Semiconductor device measurement; Switches; Training; Voltage measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2011 IEEE 29th
Conference_Location :
Dana Point, CA
ISSN :
1093-0167
Print_ISBN :
978-1-61284-657-6
Type :
conf
DOI :
10.1109/VTS.2011.5783775
Filename :
5783775
Link To Document :
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