Title :
Path Breaker: a tool for the optimal design of speed independent asynchronous controllers
Author :
Mishra, Yogesh ; Sherlekar, S.D. ; Venkatesh, G.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
Abstract :
The authors present a methodology for synthesizing speed independent asynchronous circuits from high-level continuous sampling plan (CSP)-like specifications. Instead of employing syntax-directed translation followed by local optimizing transformations on the resulting netlist, this method uses global dataflow analysis to directly produce an optimal controller. The method is shown to produce substantially smaller circuits than S.M. Burns´s and A.J. Martin´s (1988) method
Keywords :
asynchronous sequential logic; logic design; Path Breaker; asynchronous circuits; global dataflow analysis; high level continuous sampling plan-like specifications; optimal design; speed independent asynchronous controllers; syntax-directed translation; Asynchronous circuits; Circuit synthesis; Clocks; Data analysis; Delay; Design methodology; Optimal control; Optimization methods; Switches; Wire;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246273
