Title :
EURO-DAC ´92. European Design Automation Conference, EURO-VHDL ´92 (Cat. No.92CH3126-0)
Abstract :
The following topics are dealt with: asynchronous design techniques; timing issues in high-level synthesis; application of formal methods; architectural synthesis; timing analysis and verification; module generation; combinational logic synthesis; systems engineering and mechatronics; top-down physical design; finite state machine design; topological optimization in routing; design for testability; fault simulation; VHDL-related models; VHDL standardization; and formal verification in VHDL
Keywords :
circuit analysis computing; circuit layout CAD; formal specification; formal verification; logic CAD; logic circuits; VHDL; VHDL standardization; VHDL-related models; architectural synthesis; asynchronous design techniques; combinational logic synthesis; design for testability; fault simulation; finite state machine design; formal methods; formal verification; high-level synthesis; mechatronics; module generation; routing; systems engineering; timing analysis; timing issues; top-down physical design; topological optimization; verification;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg, Germany
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246274
