Fast dynamic simulation of VLSI circuits using reduced order compact macromodel of standard cells

This paper presents a dynamic simulation methodology using a reduced order compact macromodel of standard cells. The standard cell macromodels are formulated with a smaller number of state variables compared to an equivalent transistor-level implementation. This results in significant speed-ups over transistor-level simulation for large scale circuits. Such reduction in state variables also reduces memory usage. The macromodels are based on transistor equations, and simulation using these models produces results in excellent agreement (delay errors below 1%) with transistor-level simulation results. Various examples showing 1.5x-100x reduction in dynamic simulation time and 1.5x-2.8x reduction in memory usage are presented.