Title :
An analytical method for estimating SET propagation
Author :
Gangadhar, Sreenivas ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL, USA
Abstract :
In sub-micron technology, a small inaccuracy in computing the probability of occurrence of a soft error results into an unacceptable chip failure rate. A method to estimate the probability of SET propagation to the output gate at any time instant within the latching window is proposed. Its accuracy is evaluated using Monte Carlo simulations.
Keywords :
Monte Carlo methods; flip-flops; logic gates; probability; Monte Carlo simulations; SET propagation; latching window; output gate; probability; soft error; submicron technology; unacceptable chip failure rate; Attenuation; Boolean functions; Delay; Equations; Integrated circuit modeling; Logic gates; Monte Carlo methods;
Conference_Titel :
VLSI Test Symposium (VTS), 2011 IEEE 29th
Conference_Location :
Dana Point, CA
Print_ISBN :
978-1-61284-657-6
DOI :
10.1109/VTS.2011.5783783
