DocumentCode
3375962
Title
Design techniques for discrete-time delta-sigma ADCs with extra loop delay
Author
Wang, Yan ; Temes, Gábor C.
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
2159
Lastpage
2162
Abstract
In this paper, a general solution is proposed for the excess feedback loop delay issue for a discrete-time ΔΣ ADC. The corresponding low-distortion technique is also illustrated. Finally, the double-sampling ΔΣ ADC immune to the extra loop delay is described and verified through simulation.
Keywords
analogue-digital conversion; delta-sigma modulation; discrete-time ΔΣ ADC; discrete-time delta-sigma ADC; feedback loop delay; low-distortion technique; Adders; Clocks; Delay; Feedback loop; Feedforward systems; Filters; Output feedback; Power dissipation; Timing; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537225
Filename
5537225
Link To Document