Integration of SDL and VHDL for high-level digital design

A study of Specification and Description Language (SDL) and VHSIC hardware description language (VHDL) that their semantics differ considerably in several essential areas. The languages can be used to provide descriptions of systems from different and complementary viewpoints. It is shown that these viewpoints can be usefully integrated by defining them as specific views of a more general system model which defines the essentials of the system functionality and architecture. A simple class of dataflow models is selected as the general domain of system descriptions. The SDL and VHDL representations of this domain as well as the meaning of their equivalence to it are defined. These representations outline corresponding subsets of the languages to be used in describing the system model