DocumentCode :
3376131
Title :
Experiences and issues in VHDL-based synthesis
Author :
Lim, Stephen E. ; Hendry, David C. ; Yeung, Ping F.
Author_Institution :
GenRad Ltd., Fareham, UK
fYear :
1992
fDate :
7-10 Sep 1992
Firstpage :
646
Lastpage :
651
Abstract :
Synthesis systems that take VHSIC hardware description language (VHDL) as input are now widespread, and impose certain constraints, or conditions of usage, on the designer, most of which help to achieve a fast turnaround. The authors report experiences with using VHDL-based synthesis in a design environment where delivering workable circuits in short schedules is of paramount importance. Results show that a fully automated hardware description language (HDL)-based solution is not possible with present synthesis technology; designer intervention is almost always required
Keywords :
circuit CAD; specification languages; VHDL-based synthesis; VHSIC; automated hardware description language; hardware description language; workable circuits; Application specific integrated circuits; Circuit faults; Circuit synthesis; Circuit testing; Design methodology; Hardware; Logic design; Logic testing; Signal generators; Signal synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
Type :
conf
DOI :
10.1109/EURDAC.1992.246342
Filename :
246342
Link To Document :
بازگشت