Title :
A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver
Author :
Huang, Deping ; Zhou, Jin ; Li, Wei ; Li, Ning ; Ren, Junyan
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fDate :
May 30 2010-June 2 2010
Abstract :
This paper presents a Sigma-Delta fractional-N frequency synthesizer for multi-standard receiver. The synthesizer´s output range is 1.8~5.8GHz and covers the standards of DCS1800, WCDMA, TD-SCDMA, WLAN802. Ha/b/g and Bluetooth. Frequency planning is elaborately done to make sure the synthesizer meets specifications of standards mentioned above. QVCO with a proposed phase shifter is shown to have better phase noise performance and more stable oscillation. Simulated phase noise is -119dBc/Hz at 1-MHz offset from a 4.2GHz carrier. Its FOM ranges from 181 to 187. The frequency synthesizer is fabricated in TSMC 0.13um CMOS process. Average power consumption is 55.92mW.
Keywords :
Bluetooth; CMOS integrated circuits; code division multiple access; radio receivers; wireless LAN; Bluetooth; CMOS process; DCS1800; QVCO; TD-SCDMA; TSMC; WCDMA; WLAN802; fractional-n frequency synthesizer; frequency 4.2 GHz; multi-standard receiver; phase shifter; power 55.92 mW; power consumption; short range multistandard wireless receiver; Bluetooth; CMOS process; Delta-sigma modulation; Energy consumption; Frequency synthesizers; Meeting planning; Multiaccess communication; Phase noise; Phase shifters; Time division synchronous code division multiple access;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537238
