DocumentCode
3376151
Title
Fast and lossless graph division method for layout decomposition using SPQR-tree
Author
Luk, Wai-Shing ; Huang, Huiping
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2010
fDate
7-11 Nov. 2010
Firstpage
112
Lastpage
115
Abstract
Double patterning lithography is the most likely solution for 32nm and below process nodes due to its cost effectiveness. To enable this technique, layout decomposition is applied to split a layout into two non-conflicting patterns. Nevertheless, this problem is NP-hard in general, especially for layouts with random logic. Thus, high quality results are hard to be achieved in reasonable time. Previously, several graph partitioning techniques have been presented in order to speed up the process, with the tradeoff of the quality of results (QoR). We propose a graph division method that does not have this deficiency. First, we start with a conflict graph derived from a layout. Based on a data structure named SPQR-tree, the graph is divided into its triconnected components in linear time. The solutions of these components are then combined in a way that no QoR is lost. Thus, we call this method a ”lossless” method. Experimental results show that the proposed method can achieve 5X speedup without sacrificing any QoR.
Keywords
circuit optimisation; integrated circuit layout; lithography; tree searching; trees (mathematics); NP-hard; SPQR-tree; conflict graph; data structure; double patterning lithography; graph partitioning technique; layout decomposition; lossless graph division method; nonconflicting pattern; random logic; Color; Data structures; Design automation; Image color analysis; Layout; Lithography; Skeleton;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
978-1-4244-8193-4
Type
conf
DOI
10.1109/ICCAD.2010.5654108
Filename
5654108
Link To Document