Implementation of the MFCC front-end for low-cost speech recognition systems

Author

Vu, Ngoc-Vinh ; Whittington, Jim ; Ye, Hua ; Devlin, John

Author_Institution

Dept. of Electron. Eng., La Trobe Univ., Melbourne, VIC, Australia

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

2334

Lastpage

2337

Abstract

Speech recognition front-end implemented using a high-end floating-point processor is expensive both in terms of computer resources and cost. This paper presents a new small footprint MFCC front-end design that is suitable for low-cost speech recognition systems. By exploiting the overlapping nature of the input frames and by adopting a simple pipeline structure, the implemented design only utilizes approximately 10% total resources of a low-cost and modest-size FPGA device, thus leaving significant space for speech recognition post-processing.

Keywords

field programmable gate arrays; speech recognition; FPGA device; MFCC front-end; high-end floating-point processor; low-cost speech recognition systems; pipeline structure; Cepstral analysis; Cepstrum; Costs; Delay; Discrete Fourier transforms; Discrete cosine transforms; Field programmable gate arrays; Mel frequency cepstral coefficient; Signal processing algorithms; Speech recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537242

Filename

5537242