Reducing offset errors in MITE systems by precise floating gate programming

Multiple-Input Translinear Elements (MITEs) are a powerful tool for implementing translinear networks. Large-scale implementations of translinear networks have been plagued by mismatch when implemented in standard CMOS processes. The floating-gate MITE approach allows for adjustments to MITE elements post-fabrication to compensate for process-induced mismatch. In order to demonstrate this approach, a 2D-vector magnitude circuit and a cube root circuit have been synthesized to a reprogrammable architecture on a 0.35μm, commercially available, CMOS process. Sources of mismatch were predicted, identified, and then measured and compensated in silicon.