Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS)

Many applications require clock generators to synthesize accurate signals with high frequencies and very low jitter. In this paper, we present a standard-cell module to reduce jitter observed in the Free-Running Period Synthesizer (FRPS). This jitter is due to the required variation in period duration in order to obtain a precise frequency. The basic principle of the proposed design is to anticipate the occurrence of this change in period and generate an analog voltage at that point using a standard-cell digital-to-analog converter (DAC). Compared to the original FRPS, the proposed technique reduces the deterministic jitter by a factor of up to 2^N, where N is the number of bits in the DAC. The system was implemented on a Cyclone II FPGA along with discrete components and experimental results confirm that the proposed system works as expected.