DocumentCode
3376475
Title
Delay time estimate for “FAST” CMOS drivers with noisy ground reference
Author
Yang, Yaochao ; Thurairajaratnam, Aritharan ; Brews, John R. ; Prince, John L.
Author_Institution
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fYear
1995
fDate
2-4 Oct 1995
Firstpage
43
Lastpage
45
Abstract
A closed form equation to predict the signal delay of high speed CMOS drivers as a function of the Simultaneous Switching Noise (SSN) has been derived. This delay estimate agrees with the results obtained from SPICE simulations with typical driver strengths and load capacitances
Keywords
CMOS integrated circuits; delays; driver circuits; integrated circuit noise; SPICE simulation; closed form equation; high speed CMOS drivers; load capacitance; noisy ground reference; signal delay time; simultaneous switching noise; Delay effects; Delay estimation; Driver circuits; Electronics packaging; Equations; Inductance; Microelectronics; Parasitic capacitance; SPICE; Semiconductor device noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1995
Conference_Location
Portland, OR
Print_ISBN
0-7803-3034-X
Type
conf
DOI
10.1109/EPEP.1995.524690
Filename
524690
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