Design Methodology for CMOS Low-Noise Amplifiers Using Power Matching Techniques

Author

Gusad, Maria Theresa A ; Alarcon, Louis P.

Author_Institution

Dept. of Electr. & Electron. Eng., Philippine Univ., Quezon

fYear

2005

fDate

21-24 Nov. 2005

Firstpage

1

Lastpage

5

Abstract

In this paper, a methodology in designing CMOS low-noise amplifiers (LNAs) is proposed. Three power- matching techniques are considered in the design of the LNA. These are: (1) matching for maximum available gain, (2) matching for a constant gain, and (3) matching for stability. Using a 0.25 mum CMOS process, several LNA circuits employing the common-source topology with cascode configuration are designed, implemented, fabricated, and tested. The performance of LNA circuits designed using the three different techniques are characterized. Simulation and actual measurement results are also compared and analyzed to determine the capability of the simulator to predict the LNA´s overall performance at radio frequencies.

Keywords

CMOS integrated circuits; integrated circuit design; integrated circuit testing; low noise amplifiers; radiofrequency amplifiers; 0.25 mum CMOS process; CMOS amplifier testing; CMOS low-noise amplifier; LNA circuits; LNA design methodology; RF amplifier; cascode configuration; common-source topology; power matching technique; Analytical models; CMOS process; Circuit simulation; Circuit stability; Circuit testing; Circuit topology; Design methodology; Frequency measurement; Low-noise amplifiers; Predictive models;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2005 2005 IEEE Region 10

Conference_Location

Melbourne, Qld.

Print_ISBN

0-7803-9311-2

Electronic_ISBN

0-7803-9312-0

Type

conf

DOI

10.1109/TENCON.2005.300925

Filename

4084908