Modeling and simulation of multi layer gate dielectric double gate tunnel field-effect transistor (DG-TFET)

This work presents a study on Double gate Tunnel Field effect transistor (DG-TFET) with a multi layer gate dielectric, commonly known as Gate Stack (GS) architecture. An analytical model has been developed to obtain compact analytical expressions for various parameters like electron concentration in the channel, energy bands, potential and electric field at the tunneling junction. Band to band tunneling generation rate and tunneling probability has been evaluated. The performance of gate stack DG-TFET in terms of high drive current is shown through device simulation. The results obtained from analytical expressions are compared with device simulator results.