DocumentCode :
3376731
Title :
Simulation Study of Stack Gate Insulated Shallow Extension Silicon On Nothing ISE-SON MOSFET for RFICs Design
Author :
Kumari, Vandana ; Saxena, Manoj ; Gupta, Mridula ; Gupta, R.S.
Author_Institution :
Dept. of Electron. Sci., Univ. of Delhi, New Delhi, India
fYear :
2011
fDate :
14-16 Jan. 2011
Firstpage :
286
Lastpage :
291
Abstract :
In this paper, we present the simulation study of RF linearity of gate stacked Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET and compared it with the Insulated Shallow Extension (ISE) and silicon On Nothing (SON) MOSFET using ATLAS 3D device simulator. ISE architecture along with the SON MOSFET proves to be better candidate for suppression of Short Channel Effects (SCEs).
Keywords :
MOSFET; electronic engineering computing; radiofrequency integrated circuits; ATLAS 3D device simulator; ISE-SON MOSFET; RFIC design; short channel effect suppression; stack gate insulated shallow extension silicon on nothing MOSFET; Linearity; MOSFET circuits; Neodymium; Performance evaluation; Transistors; ATLAS 3D; Linearity; Stack Gate; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Students' Technology Symposium (TechSym), 2011 IEEE
Conference_Location :
Kharagpur
Print_ISBN :
978-1-4244-8941-1
Type :
conf
DOI :
10.1109/TECHSYM.2011.5783831
Filename :
5783831
Link To Document :
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