The fast optimal voltage partitioning algorithm for peak power density minimization

Increasing transistor density in nanometer integrated circuits has resulted in large on-chip power density. As a high-level power optimization technique, voltage partitioning is effective in mitigating power density. Previous works on voltage partitioning attempt to address it through minimizing total power consumption over all voltage partitions. Since power density significantly impacts thermal-induced reliability, it is also desired to directly mitigate peak power density during voltage partitioning. Unfortunately, none of the existing works consider this. This paper proposes an efficient optimal voltage partitioning algorithm for peak power density minimization. Based on novel algorithmic techniques such as implicit power density binary search, the algorithm runs in O(n log n + m² log² n) time, where n refers to the number of functional units and m refers to the number of partitions/voltage levels. Our experimental results on large testcases demonstrate that large amount of (about 9.7×) reduction in peak power density can be achieved compared to a natural greedy algorithm, while the algorithm still runs very fast. It needs only 14.15 seconds to optimize 1M functional units.