DocumentCode
3376937
Title
An interstage correlated double sampling technique for switched-capacitor gain stages
Author
Rajaee, Omid ; Hu, Yue ; Gande, Manideep ; Musah, Tawfiq ; Moon, Un-Ku
Author_Institution
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
1252
Lastpage
1255
Abstract
An Interstage Correlated Double Sampling technique is proposed. This new technique avoids the additional thermal noise penalty and the overall feedback factor degradation introduced by the conventional correlated double sampling techniques. In the proposed architecture, a two-stage amplifier is employed and the correlated double sampling is applied to the input of the second gain-stage. The superior noise performance and the gain enhancement of the proposed architecture to the conventional CDS technique is demonstrated in this paper.
Keywords
operational amplifiers; switched capacitor networks; CDS technique; feedback factor degradation; interstage correlated double sampling technique; switched capacitor gain stages; thermal noise penalty; two-stage amplifier; Additive noise; Capacitors; Computer architecture; Feedback; Moon; Power amplifiers; Sampling methods; Thermal degradation; Thermal factors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537279
Filename
5537279
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