ASIC implementation of a 512-point FFT/IFFT processor for 2D CT image reconstruction algorithm

The CT scan medical imaging requires huge amount of computations for reconstructing the images. Modified Fast Radon Transform (MFRT) uses FFT based parallel algorithm for reconstruction of 2D/3D CT images from its sonogram data using convolution operation by concurrent 1D FFT/IFFT and matrix multiplications. To achieve optimum hardware utilization with low power consumption an FFT module, based on iterative radix-2 decimation in frequency (DIF) algorithm, has been designed and implemented. The module has been designed in such way so that it can also be used for IFFT computation only by changing a single parameter. To compute the FFT, the twiddle factor has been calculated using Coordinate Rotation Digital Computer (CORDIC), by steering the data properly in the butterfly structure. The synthesized frequency of FFT/IFFT module is 220 MHz and gate count is 1,040,136 using 130 nm faraday digital libraries. The power has been analyzed using prime power and the value of the power consumption is 15mW. The designed FFT/IFFT ASIC chip is very much suitable for low-area and low power biomedical applications like CT image reconstruction, Doppler wave spectrogram etc.