Design and analysis of tree-multiplier using single-clocked energy efficient adiabatic Logic

Author

Chanda, M. ; Kundu, S. ; Adak, I. ; Dandapat, A. ; Rahaman, H.

Author_Institution

BESU, VLSI Technol. Lab., Howrah, India

fYear

2011

fDate

14-16 Jan. 2011

Firstpage

232

Lastpage

236

Abstract

In this paper ultra low power characteristics of the newly proposed energy efficient adiabatic Logic (EEAL) is investigated. EEAL is based on differential cascode voltage swing (DCVS) logic, uses only a single sinusoidal source as supply-clock. With minimal clocking overhead this proposed logic eliminates the floating output problem and enhances the energy efficiency significantly. An EEAL based 8×8 tree multiplier by 4-2 compressor circuits have been implemented in a TSMC 0.18 μm CMOS technology. CADENCE simulation shows that EEAL based multiplier circuit consumes only 25%-30% of total energy consumed by single clocked adiabatic logics. Both simulation and measurement results verify the functionality of such logic, making it suitable for implementing energy-aware and performance-efficient sequential circuit.

Keywords

CMOS logic circuits; logic design; low-power electronics; CADENCE simulation; CMOS technology; compressor circuits; differential cascode voltage swing logic; single-clocked energy efficient adiabatic logic; size 0.18 mum; tree multiplier; ultra low power characteristics; CMOS integrated circuits; CMOS technology; Clocks; Inverters; Propagation losses; Variable speed drives; 4-2 compressor; Adiabatic logic; energy efficiency; single-clock; tree multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Students' Technology Symposium (TechSym), 2011 IEEE

Conference_Location

Kharagpur

Print_ISBN

978-1-4244-8941-1

Type

conf

DOI

10.1109/TECHSYM.2011.5783851

Filename

5783851