A Reconfigurable RF Circuit Architecture for Dynamic Power Reduction

This paper proposes a reconfigurable RF circuit architecture for dynamic power reduction. The architecture consists of RF circuits and a control circuit. The RF circuits can be reconfigured by bias voltages of transistors and variable passive devices, and the RF circuit block can also be switched dynamically. Analog RF circuits usually have redundant margin in circuit performance to compensate PVT variations, and it also causes redundant power consumption. The reconfigurable RF circuit can reduce power consumption by the dynamic reconfiguration, which compensates the performance margin. We demonstrate dynamic power reduction for opamp and LNA.