Title :
Two-step junction-splitting SAR analog-to-digital converter
Author :
Yu, Wenhuan ; Lin, Jiaming ; Temes, Gabor C.
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
fDate :
May 30 2010-June 2 2010
Abstract :
A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analog-to-digital converters (SAR ADCs). Two junction-split binary-weighted capacitor arrays are used in a coarse/fine quantization scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC.
Keywords :
analogue-digital conversion; capacitors; capacitor area; coarse-fine quantization scheme; power consumption; successive-approximation register; two junction-split binary-weighted capacitor arrays; two-step junction-splitting SAR analog-to-digital converter; Analog-digital conversion; Capacitors; Circuits; Energy consumption; Phased arrays; Quantization; Sampling methods; Signal resolution; Switches; Voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537325
