A novel sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation

This paper describes a novel sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation which eliminates loop bandwidth limit in traditional fractional-N synthesizers. The proposed synthesizer utilizes a delay line after the reference signal to compensate phase errors and achieves at least 19dB fractional spur and quantization noise improvement if a delay line with 32ps delay resolution is employed in the phase-locked loop with 180kHz loop bandwidth at 3.5GHz synthesized frequency. The improvement can be further enhanced with advanced process with the improved delay resolution.