A radix-3 SAR analog-to-digital converter

A radix-3, 4-trits, Ternary Successive Approximation Analog to Digital Converter (TSAR-ADC), with an option to extend to radix-N approaches is presented. Proposed TSAR-ADC architecture generates 4 ternary outputs spanning 3⁴ = 81 binary levels linearly for a rail-to-rail input voltage ranging from 0 to 3.3V. The radix-3 TSAR-ADC takes only 4 clock cycles for producing 4-trits or 6.33 bits in comparison to 7 clock cycles in a conventional binary SAR converter. The ADC is designed and fabricated on a 0.35μm double poly, three level metal CMOS technology, achieving less than 1 LSB INL, 0.8 LSB of DNL, consuming 1.6-mW from a 3.3-V supply.