Trade-offs in scan path and BIST implementations for RAMs

Scan path testing has the drawback that it increases considerably the test length. The authors first present an original technique which allows RAM scan path testing without increasing the test length. Then they compare several address generation, test data generation and output response verification techniques for RAM BIST, scanpath and BIST schemes. Automatic generation tools have been implemented for these schemes and allow to select the more efficient ones. This way one can reduce the design effort and satisfy several constraints like low area overhead, high fault coverage and low test length for embedded RAMs