An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

Author

Ikeda, Mitsuo ; Kondo, Toshio ; Nitta, Koyo ; Suguri, Kazuhito ; Yoshitome, Takeshi ; Minami, Toshihiro ; Naganuma, Jiro ; Ohura, T.

Author_Institution

NTT Human Interface Labs., Yokosuka, Japan

fYear

1999

fDate

9-12 March 1999

Firstpage

44

Lastpage

50

Abstract

This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in a 0.25 /spl mu/m four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

Keywords

CMOS digital integrated circuits; circuit CAD; code standards; data compression; digital signal processing chips; hardware-software codesign; high definition television; integrated circuit design; large scale integration; low-power electronics; pipeline processing; telecommunication computing; video coding; 0.25 micron; CMOS IC; DVD recorders; HDTV encoders; MPEG-2 video encoder LSI; PC-card encoders; flexible data-transfer; four-metal CMOS process; low power consumption; scalability; single-chip encoder; three-layer cooperative architecture; Discrete cosine transforms; HDTV; Large scale integration; Motion compensation; Motion control; Motion estimation; Quantization; Radio control; Scalability;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Conference_Location

Munich, Germany

Print_ISBN

0-7695-0078-1

Type

conf

DOI

10.1109/DATE.1999.761095

Filename

761095