Peak power estimation using genetic spot optimization for large VLSI circuits

Author

Hsiao, Michael S.

Author_Institution

Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA

fYear

1999

fDate

1999

Firstpage

175

Lastpage

179

Abstract

Estimating peak power involves optimization of the circuit´s switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times

Keywords

VLSI; circuit optimisation; digital integrated circuits; genetic algorithms; logic CAD; sequential circuits; circuit switching function optimization; delay model; genetic spot optimization; large VLSI circuits; large sequential circuits; maximum power potential; peak power estimation; sequential benchmark circuits; tight peak power bounds; Combinational circuits; Delay estimation; Genetics; Portable computers; Power dissipation; Power measurement; Sequential circuits; Switches; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings

Conference_Location

Munich

Print_ISBN

0-7695-0078-1

Type

conf

DOI

10.1109/DATE.1999.761115

Filename

761115