Title :
Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits
Author_Institution :
Dept. of Inf. Eng., Univ. of Siena, Siena, Italy
fDate :
May 30 2010-June 2 2010
Abstract :
In this paper, subthreshold static CMOS logic is analyzed in terms of DC noise immunity in a closed form for the first time. Simplified circuit models of MOS transistors in subthreshold are developed to gain a deeper understanding of the degradation in the DC characteristics under ultra-low voltages, as well as its dependence on design and process parameters. The noise margin is explicitly evaluated and modeled with a simple expression. The impact of PMOS/NMOS imbalance is also explicitly analyzed. Results are validated with simulations in a 65-nm CMOS technology.
Keywords :
CMOS logic circuits; MOSFET circuits; integrated circuit modelling; logic design; CMOS logic circuits; DC noise immunity; MOS transistors; NMOS; PMOS; circuit models; closed-form analysis; size 65 nm; CMOS logic circuits; CMOS technology; Circuit noise; Immune system; MOS devices; MOSFETs; Noise robustness; Process design; Semiconductor device modeling; Threshold voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537340
