Ultra low voltage static carry generate circuit

In this paper we present an ultra low-voltage static CMOS carry generate circuit. The circuit may operate at supply voltages below the inherent threshold voltage of the transistors while maintaining a current level of transistors operating in strong inversion. The circuit show an improved performance compared to standard CMOS in terms of delay. Preliminary results indicate a reduced delay to approximately 1/10 of a standard CMOS design. A 32 bit serial carry chain is simulated and the delay is compared to a traditional CMOS carry chain. Simulated data for a ST 90 nm CMOS process are included.