Title :
Ultra low voltage static carry generate circuit
Author_Institution :
Nanoelectron. Dept. of Inf., Univ. of Oslo, Oslo, Norway
fDate :
May 30 2010-June 2 2010
Abstract :
In this paper we present an ultra low-voltage static CMOS carry generate circuit. The circuit may operate at supply voltages below the inherent threshold voltage of the transistors while maintaining a current level of transistors operating in strong inversion. The circuit show an improved performance compared to standard CMOS in terms of delay. Preliminary results indicate a reduced delay to approximately 1/10 of a standard CMOS design. A 32 bit serial carry chain is simulated and the delay is compared to a traditional CMOS carry chain. Simulated data for a ST 90 nm CMOS process are included.
Keywords :
CMOS logic circuits; carry logic; low-power electronics; transistors; CMOS design; serial carry chain; transistor threshold voltage; ultralow-voltage static carry generate circuit; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Delay; Inverters; Logic circuits; Low voltage; MOSFETs; Threshold voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537346
