DocumentCode :
3378082
Title :
A novel multiply-by-three circuit
Author :
Foster, Caxton ; Riseman, Edward ; Stockton, Fred ; Wogrin, Conrad
Author_Institution :
Computer Science Department, University of Massachusetts Amherst, Massachusetts
fYear :
1975
fDate :
19-20 Nov. 1975
Firstpage :
185
Lastpage :
187
Abstract :
Recently, while considering the connection of a 48 bit word computer to a 16 bit computer, we felt the need for a fast and inexpensive device that would multiply a binary address by a factor of three. Since 3N = N + 2N, there is an obvious solution of providing a normal adder circuit and presenting one set of inputs with N and the other with N-shifted left one place. But, there is a great deal of redundancy here since knowing one input we have complete knowledge of the other.
Keywords :
Adders; Computers; Equations; Logic gates; Marine animals; Propagation delay; Redundancy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Arithmetic (ARITH), 1975 IEEE 3rd Symposium on
Conference_Location :
Dallas, TX, USA
Type :
conf
DOI :
10.1109/ARITH.1975.6156983
Filename :
6156983
Link To Document :
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