Combinational ATPG theorems for identifying untestable faults in sequential circuits

The authors present two theorems for identifying untestable faults in sequential circuits. The first, single-fault theorem, states that if a single fault in a combinational array is untestable then that fault is untestable in the sequential circuit. The array replicates the combinational logic and can have any finite length. The present state inputs of the left-most block are assumed completely controllable. The next state outputs of the right-most block are considered observable. A combinational test pattern generator determines the detectability of single faults in the right-most block. The second (multi-fault) theorem states that an untestable multi-fault in the array corresponds to an untestable fault in the sequential circuit. For the array with a single block both the theorems identify combinational redundancies. Experiments on ISCAS benchmarks show that using a small array size (typically, two to four blocks) a large number of sequentially untestable faults can be identified