Emitter coupled logic testability analysis and comparison with CMOS & BiCMOS circuits

The logic behavior and performance of an ECL OR/NOR gate under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage. Performance degradation faults such as delay, current and voltage transfer characteristics (VTC) or noise margin (NM) faults are analyzed as applied to these gates. It is shown that a combination of logical fault testing with delay fault testing yields the highest fault coverage for BiCMOS and CMOS gates. However, for an equivalent ECL gate, logical together with VTC fault testing methods promises a fault coverage of around 98%