Design of pipelined FIR filter with MSB-first multiplier

The pipelined method is a common and an inexpensive technique to implement analog-to-digital conversion. The conversion using this method consists of several cycles. The coarser quantization is performed first before the finer quantizations. As a result, this method generates output streams with the most-significant bit (MSB) being first. Subsequent data processing that uses MSB-first scheme could start computation before the complete conversion result is present, and thereby minimize the total computation time. This paper presents two designs of pipelined FIR filters which utilize a bit-serial multiplier that accepts stream inputs with MSB-first from a pipelined ADC. These two possible designs are compared with respect to hardware cost and speed when they are used in designing FIR filters