Comparison of VHDL/synthesis and graphical methods for top-down design

Many engineers find that VHDL descriptions of electronic circuits are not as readily understood as schematics. This is mainly because the functionality of the circuit is lost in the code necessary to establish the data path and instantiate the components using VHDL. As electronic designs, particularly ASICs, become larger and more complex top-down design methods become more and more important. A user-friendly approach to top-down design is essential to convince would-be users to change their current methods. This paper proposes a system which combines VHDL functional descriptions with schematics to give a more user-friendly top-down design system