Limitations of synthesis techniques for time-critical digital design

Designers were unable to indicate time-critical paths in a digital system when using first generation synthesis tools. It was usual to have to revert to traditional techniques for those parts of a circuit which needed to be optimised for delay. This paper will present the author´s experiences in designing a fault-tolerant communications controller using ViewLogic´s PowerView VHDL targeted to a Xilinx FPGA. As minimising delay was a design requirement, it was necessary to use traditional schematic design techniques for the critical paths