Current vs. logic testability of bridges in scan chains

Comparison between current and voltage testing in a scan-path flip-flop affected by single bridging defects is presented. Defects obtained by inductive fault analysis (IFA) have been classified depending on the location within the scan cell and its electrical behaviour has been simulated using HSPICE. Current (I_ddq) testing of zero resistance bridges covers only 92% of the realistic bridges obtained by IFA. The remaining 8%, can be detected by logic (voltage) testing. For realistic bridges with resistance above 2 Ω, current testing is highly efficient achieving 100 % coverage with the appropriate I_ddq sensor. On the contrary, logic testing is highly inefficient in detecting resistive bridges some of which may cause timing degradation in spite of error free quiescent behaviour