Using EDIF in IC testing: experience from the Everest project

Author

Baker, K. ; Morren, R. ; Wahl, M. ; Verhelst, B.

Author_Institution

Philips Res. Labs., Eindhoven, Netherlands

fYear

1993

fDate

19-22 Apr 1993

Firstpage

434

Lastpage

443

Abstract

Without a standard for describing test vectors, timing and levels it is a cumbersome process to take test data from an ATPG to a simulator or from a simulator to an ATE. From the electronic industries in Europe, USA and Japan, many people have worked together under the auspices of the EIA to create a provisional test view in EDIF (electronic design interchange formats). This paper evaluates an early version (i.e. EDIF 2 0 31) of this standard both from a software developer´s view and from a user´s view via a large scale benchmark performed by the Everest project

Keywords

VLSI; automatic test equipment; automatic testing; design for testability; electronic data interchange; integrated circuit testing; performance evaluation; production testing; software engineering; standards; ATE; ATPG; EDIF; EIA; Europe; Everest project; IC testing; Japan; USA; electronic design interchange formats; large scale benchmark; standard; test vectors; Automatic test pattern generation; Electronic equipment testing; Electronics industry; Europe; Industrial electronics; Integrated circuit testing; Software performance; Software standards; Standards development; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1993. Proceedings of ETC 93., Third

Conference_Location

Rotterdam

Print_ISBN

0-8186-3360-3

Type

conf

DOI

10.1109/ETC.1993.246588

Filename

246588