Title :
Experimental results on aliasing errors in circular BIST design
Author :
Kothari, Rajiv D. ; Ha, Dong Sam
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Although many analyses on aliasing errors have been reported, no definite experiments has been reported on aliasing probabilities under built-in self-test (BIST) environment. In this paper, the authors present experimental results on the aliasing probability of the circular BIST design technique. Among 23 ISCAS89 benchmark circuits experimented, aliasing errors were detected in only 2 of the 23 circuits at the end of the application of 2000 clocks. However, 11 circuits encountered aliaising errors during the period of the 2000 clocks. The average and maximum aliasing probability observed in an 8 and a 16 bit signature analysis registers for the 23 circuits are also presented. No aliasing errors were observed for a 32 bit signature analysis register
Keywords :
built-in self test; design for testability; digital simulation; fault location; logic design; probability; 23 ISCAS89 benchmark circuits; 32 bit signature analysis register; aliasing errors; aliasing probabilities; built-in self-test; circular BIST design; simulation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Compaction; Costs; Logic testing; Registers; Test pattern generators;
Conference_Titel :
European Test Conference, 1993. Proceedings of ETC 93., Third
Conference_Location :
Rotterdam
Print_ISBN :
0-8186-3360-3
DOI :
10.1109/ETC.1993.246593
