An area efficient design methodology for SEU tolerant digital circuits

Author

Purohit, Sohan ; Harrington, David ; Margala, Martin

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Massachusetts Lowell, Lowell, MA, USA

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

981

Lastpage

984

Abstract

This paper presents a new circuit design style for radiation hardened digital circuits. The proposed design methodology is based on the well known DCVSL circuit style. The original DCVSL has been modified to build in robustness against single event upsets due to particle strikes. The paper presents simulation results for logic gates and arithmetic circuits built using the proposed design scheme. The circuits were found to have area savings of about 26% over their static CMOS counterparts at the cost of 7% extra delay. The design style described in this paper was found to be extremely reliable with 100% SEU mitigation for a wide spectrum of charge and current profiles at relatively lower cost than previously published circuit schemes for SEU mitigation.

Keywords

digital arithmetic; logic design; logic gates; radiation hardening (electronics); DCVSL circuit style; SEU mitigation; SEU tolerant digital circuits; area efficient design methodology; arithmetic circuits; circuit design style; differential cascode voltage swing design; logic gates; radiation hardened digital circuits; single event upset; static CMOS counterparts; CMOS logic circuits; Circuit simulation; Circuit synthesis; Costs; Design methodology; Digital circuits; Logic gates; Radiation hardening; Robustness; Single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537381

Filename

5537381