Methodologies for sub-1nm EOT TDDB evaluation

Measuring and understanding TDDB reliability in sub-1nm EOT dielectrics is both a practical and scientific challenge. We present three different methods for the experimental determination of the SBD and wearout parameters needed to construct an all-in-one TDDB reliability prediction consisting of a SBD-free region, a leakage current-dominated region and a HBD-limited region. We demonstrate these methods on several sub-1nm EOT high-k/metal gate nMOS and pMOS devices and evaluate their advantage and disadvantages. We also discuss the validity and interpretation of the SBD/wearout model, confronting it with experiments that demonstrate how SBD paths can be annealed by reversing the stress polarity.