Re-investigation of gate oxide breakdown on logic circuit reliability

Gate oxide breakdown has been studied in the circuit-like patterns, i.e. e-Fuse arrays and two-stage inverter circuit. It is observed that time-dependent dielectric breakdown (TDDB) lifetime of eFuse chip is larger compared to discrete devices. Gate oxide breakdown study using two-stage inverter circuit (1^st-stage I/O N/PMOS worked as current limiting transistors and 2^nd-stage core N/PMOS is stressed transistors) reveals that, even by applying a significant high voltage stress (≤ 3×Vdd) on stressed device, the stress device will suffer only soft breakdown not a hard breakdown and it is independent with the current drive capability of current limiting transistors. Soft breakdown results in very small voltage drop across the current limiting device (i.e. between source and drain terminals), which will have negligible impact on the circuit functionality. It suggests circuit functionality will be immune from gate oxide breakdown in normal circuit operating condition, i.e. V_dd of ~1V, and designers will get extra reliability margin. Our HSPICE simulation results on ring oscillator (RO) also suggest the logic circuit functionality immunity with gate oxide breakdown.