Title :
New methods for parallel pattern fast fault simulation for synchronous sequential circuits
Author :
Mojtahedi, Mehrdad ; Geisselhardt, Walter
Author_Institution :
Duisburg Univ., Germany
Abstract :
The authors present COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED is based on coupling a parallel pattern simulator with a non-parallel simulator. COMBINED runs substantialy faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator
Keywords :
digital simulation; fault location; logic testing; sequential circuits; COMBINED; ISCAS-89 benchmark circuits; logic testing; parallel pattern fast fault simulation; synchronous sequential circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Coupling circuits; Discrete event simulation; Electrical fault detection; Fault detection; Sequential circuits; Switches;
Conference_Titel :
European Test Conference, 1993. Proceedings of ETC 93., Third
Conference_Location :
Rotterdam
Print_ISBN :
0-8186-3360-3
DOI :
10.1109/ETC.1993.246617
